Sr. Circuit Memory Design Engineer

Location: Irvine, CA, United States
Job Duties:
Engineer will be responsible for design, implementation, and verification of embedded memory compilers, including schematic and layout design and verification, LVS, DRC, parasitic extraction, spice simulation, software compiler implantation, documentation, verilog modeling, monte-carlo simulation, and quality-assurance.
Job Qualifications:
Looking for Senior Circuit Design Engineer with 3-8 years experience in transistor-level circuit design. BSEE required, MSEE preferred. Candidate should have strong background in sub-28nm, low-power circuit design with a good understanding of device level physics and experience with silicon debug. Experience with schematic capture, layout, LVS (layout versus schematics) & DRC (design rule check) verification is a must. Knowledge of ASIC design flow and/or Verilog is a bonus.
Candidate should have strong software skills, specifically perl scripting and the ability to understand existing code and write own custom scripts. A candidate with prior industry experience (as opposed to just academic experience) with memory design would be highly valued.
Mentor EDA tool experience - Candidate will be dealing with Calibre, Eldo, Pyxis Design Manager (Formerly ICstudio) and Questa (Formerly ModelSim). Irvine location is preferred, but remote site is a possibility.

Additional requirements and capabilities:
1. Able to communicate effectively and manage a small team of design engineers.
2. Experience with memory compiler software.
3. Experience with memory leaf cell design.
Melissa Galloway
ProEnlist, LLC
720-358-4638 Direct
720-507-2417 SMS 

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